Ultra-thin near-hermetic package based on rainier

ABSTRACT

A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals.

The present application is a divisional of U.S. patent application Ser.No. 11/803,006, filed on May 11, 2007, and is set to issue as U.S. Pat.No. 8,508,036 on Aug. 13, 2013, the disclosure of which is incorporatedherein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to microelectronic packages used formicroelectronic chip packaging, and methods for making microelectronicpackages for microelectronic chip packaging.

Semiconductor chips are commonly provided in packages that facilitatehandling of the chip during manufacture and during mounting of the chipon an external substrate such as a circuit board, wiring board or othercircuit panel. For example, many semiconductor chips are provided inpackages suitable for surface mounting. Such packages which can besurface mounted can provide reduced thermal resistance as well as anextremely low electrical resistance between the chip and the package andwiring for external connection. Numerous packages of this general typehave been proposed for various applications. Certain types of packageshave been developed which utilize a microelectronic component having aflexible dielectric substrate having conductive traces disposed thereon.In such an arrangement, electrically conductive posts, pillars or otherconnection elements project from a surface of the flexible substrate.Each post is connected to a portion of one of the traces, the tracesbeing arranged on the other surface of the flexible surface, and areconfigured to be connected with a chip.

This type of microelectronic component has various applications and canbe used in a number of different microelectronic package arrangements.As disclosed in certain preferred embodiments of U.S. patent applicationSer. Nos. 11/014,439; 10/985,119; and 10/985,126, the disclosures ofwhich are incorporated by reference herein, one such microelectronicpackage can include a microelectronic element such as a semiconductorchip and a microelectronic component comprising a flexible substratespaced from and overlying a first face of the microelectronic element.Such a component can include a plurality of conductive posts extendingfrom the flexible substrate and projecting away from the microelectronicelement, at least some of the conductive posts being electricallyinterconnected with said microelectronic element. Additionally, such apackage can include a plurality of support elements disposed between themicroelectronic element and the substrate and supporting the flexiblesubstrate over the microelectronic device.

Despite these advances in the art of semiconductor package assembliesand existing hermetic packages, still further improvements in makingmicroelectronic components would be desirable. A packaging method anddevice is needed to fabricate a compact, thin, and substantiallyhermetic package.

SUMMARY OF THE INVENTION

According to an aspect, a microelectronic package is provided.Preferably, the microelectronic package includes a dielectric layerhaving top and bottom surfaces, the dielectric layer having terminalsexposed at at least one of the surfaces. In addition, themicroelectronic package includes a metallic wall bonded to thedielectric layer and projecting upwardly from the top surface of thedielectric layer and surrounding a region of the top surface, a metalliclid bonded to the wall and extending over the region of the top surfaceso that the lid, the wall and the dielectric layer cooperatively definean enclosed space. Furthermore, a microelectronic element disposedwithin the space and electrically connected to the terminals.

Another aspect is a method of making a microelectronic package. Themethod desirably comprises the step of providing a dielectric layerhaving top and bottom surfaces, terminals exposed at at least one of thesurfaces, and a wall projecting upwardly from the top surface. Themethod according to this aspect preferably also includes the step ofmounting a microelectronic element over a region of the top surfacesurrounded by the dielectric layer and electrically connecting themicroelectronic element to at least some of the terminals, and a furtherstep of bonding a metallic lid to the wall so that the lid extends overthe microelectronic element and the microelectronic element.

A further aspect provides a method of making a microelectronic chipcarrier. A method according to this aspect desirably includes providinga composite metallic plate including a base layer of a metal and aconductive layer; etching the base layer to form a wall; and etching theconductive layer to separate the conductive layer into individualconductive elements. The method most preferably further includes thestep of uniting the conductive elements and wall with a dielectric layerso that the wall projects upwardly away from the dielectric layer andencircles a region of the dielectric layer, and so that the conductiveelements are carried on the region of the dielectric layer encircled bythe wall. For example, the step of uniting the conductive elements andthe wall with the dielectric layer may include uniting the dielectriclayer with the composite metallic plate after etching the conductivelayer to separate the conductive layer into individual conductiveelements, and before etching the base layer to form the wall.Alternatively, the step of uniting the conductive elements and the wallwith the dielectric layer may be performed by uniting the dielectriclayer with the composite metallic plate before etching the base layer toform the wall, and the step of etching the conductive layer to form theindividual conductive elements may be performed during or after etchingthe base layer to form the wall.

These and other features, and advantages, will be more clearlyunderstood from the following detailed description taken in conjunctionwith the accompanying drawings. It is important to point out that theillustrations may not necessarily be drawn to scale, and that there maybe other embodiments which are not specifically illustrated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1H are diagrammatic sectional views of a chip carrier accordingto a first embodiment during various stages of a manufacturing process;

FIG. 1I is a top plan view of the chip carrier at the stage ofmanufacture shown in FIG. 1F.

FIG. 2 is a diagrammatic sectional view depicting the completed packageusing the chip carrier formed according of FIGS. 1C-1I;

FIGS. 3A-3F are diagrammatic sectional views of a package according toanother embodiment during various stages of a manufacturing processaccording to a further embodiment;

FIG. 4 is a diagrammatic top view depicting components in a method inaccordance with a further embodiment;

FIG. 5 is a diagrammatic sectional view along line 5-5 in FIG. 4;

FIG. 6 is a diagrammatic sectional view of a package according toanother embodiment;

FIG. 7 is a diagrammatic sectional view of a package according to yetanother embodiment;

FIGS. 8 and 9 are fragmentary diagrammatic sectional views depictingportions of packages according to still further embodiments;

FIG. 10 is a diagrammatic top view showing a portion of a packageaccording to yet another embodiment.

DETAILED DESCRIPTION

FIGS. 1A-1I show a manufacturing method for making the chip carrier 16together with the metallic walls 20 shown in FIG. 2, in accordance witha first embodiment. The chip carrier 16 serves as a base for a hermetic,airtight, or near-hermetic package 10. The manufactured package 10 shownas an exemplary embodiment in a possible end state in FIG. 2.

A manufacturing process according to this embodiment starts with asubassembly or composite metallic plate 166 (FIG. 1A) including anetch-resistant layer 162 having an upper surface 159 and a lower surface161. The metallic plate 166 also includes a base layer 160 having anupper surface and a lower surface. The etch-resistant layer 162 isdisposed on the base layer 160, such that the upper surface 163 of theetch-resistant layer 162 confronts the lower surface 161 of the baselayer 160. Only a small portion of subassembly 166 is shown in FIG. 1A.The subassembly typically is provided as a large sheet or tape havingarea sufficient to form numerous chip packages

As used in this disclosure, terms such as “upwardly,” “upper,” “top,”“downwardly,” “lower,” “bottom,” “vertically,” and “horizontally” shouldbe understood as referring to the frame of reference of the elementspecified and need not conform to the normal gravitational frame ofreference. In FIGS. 1A-1B, the upward direction is the direction towardsthe top of the drawing.

The etch-resistant layer 162 is preferably an etch-resistant layerconstructed from a metal such as nickel or other metal which resistsattack by an etching agent, which agent will readily attack the metal ofbase layer 160. The etch-resistant layer 162 is relatively thin and incertain preferred embodiments is a fraction of a micron to a few micronsthick as, for example, 1 micron thick. The base layer 160 is constructedfrom conductive material such as copper. In comparison to theetch-resistant layer 162, the base layer 160 is relatively thick and incertain preferred embodiments the base layer has a thicknessapproximately between 50 μm to 1500 μm. Since the base layer 160 willform metallic walls that will encircle a recess holding amicroelectronic device, the base layer 160 can be high enough to surpassan upper edge of a microelectronic device 28 that has to be packaged.Merely by way of example, the subassembly or plate 166 may be formed byplating the etch-resistant layer onto the top surface of the base layer160.

Once the subassembly or composite plate 166 has been formed, theetch-resistant layer 162 may be selectively patterned, as shown in FIG.1B, and also shown from a top perspective in FIG. 1I. In one suchtechnique, the etch-resistant layer 162 is subjected to a wet-etchingprocess to remove unwanted portions of the etch resistant layer 162. Theetchant used in this step may be selected so that it does notsubstantially attack the base layer 160. For example, where the baselayer 160 is formed from copper and the etch-resistant layer 162 isformed from nickel, an etchant including HCl may be used to remove thenickel. Alternatively or additionally, the process may be monitored andterminated promptly after the unwanted portions of the etch-resistantlayer are removed.

In an alternate embodiment, the etch-resistant layer 162 may beselectively plated onto desired portions of the base layer 160 as forexample using a mask and plate technique.

The etching of the etch-resistant layer 162 exposes portions of thelower surface of the base layer 160. As shown in FIG. 1B, the portionsof the etch-resistant layer 162 not etched away may form a skeletonpattern 129. For example, the etch-resistant layer 162 may be a nickellayer, the etchant may be based on Sulfuric Acid and Hydrogen Peroxide.The skeleton pattern, seen at a later stage of manufacture in FIG. 1I,includes numerous islands 124 a, 124 b, and 124 c, each having anelongate trace-forming portion 130 and a circular terminal-formingportion 132. The elongate portions 130 are contiguous with the circularportions 132.

Although only a small number of islands 124 a, 124 b, and 124 c areshown for clarity of illustration, in actuality, a much higher number ofislands may be employed. Also, the patterned islands 124 a, 124 b, and124 c may have different geometric configurations and/or interconnectingbridges, which connect one island to another. As will be describedbelow, the shape and positioning of skeleton pattern 129 employed isdependent on a desired layout of conductive features such as terminalsand traces in the finished package 10.

With reference to FIG. 1C, once the etch-resistant layer 162 has beenpatterned, a conductive layer 164 may be disposed over the remainingportions of the etch-resistant layer and the exposed portions of theupper surface of the base layer 160. Thus, the conductive layer 164 ispositioned adjacent to the upper surface of the remaining portions ofthe etch-resistant layer 162, now forming a skeleton pattern 129. Theconductive layer 164 is preferably comprised of a metal such as copper,and is plated or laminated onto the various surfaces. The conductivelayer 164 is preferably planar. The conductive layer 164 may have veryshallow depressions (not shown) corresponding to the gaps between theislands 124 a, 124 b, and 124 c, in the etch-resistant layer. Any suchdepressions will have a depth no more than the thickness of theetch-resistant layer 162, and most typically less than the thickness ofthe etch-resistant layer 162. Thus, any such depressions will have adepth on the order of a few microns or less and typically 1 micron orless. Conductive layer 164 has a thickness equal to the desiredthickness of contact pads 24 or other conductive elements in thefinished chip carrier 16, preferably between 5 and 50 microns, mosttypically between 10 and 20 microns.

Referring to FIG. 1D, a dielectric layer 168 is positioned adjacent theconductive layer 164 with a lower surface 33 of the dielectric layer 168facing away from conductive layer 164. The dielectric layer 168 may becomprised of many different materials. Preferably, the material isflexible. Where a hermetic or near-hermetic package is desired, thematerial desirably has low moisture absorption and low diffusion. Forexample, a high-performance polymeric dielectric can be used for thedielectric layer 168, such as liquid crystal polymer (LCP). LCP layersare virtually impermeable by liquids and gases. In addition, LCP layershave a very low moisture absorption coefficient and a constantdielectric coefficient and low loss factor over a wide frequency range.The LCP layers present other advantages that are desirable for the useas substrate material for a hermetic or near-hermetic package, such asgood dielectric strength, low coefficient of thermal expansion,providing dimensional and electrical stability under thermal cycles.Suitable LCP materials that can be used include VECTRA™ (from themanufacturer, Hoechst-Celanese), XYDAR™ (Amoco), and ZENITE™ (DuPont).

The dielectric layer 168 may be adhered to the conductive layer 164using an adhesive, which may be a separate layer or incorporated intothe dielectric layer. The dielectric layer 168 may have any thickness,but most typically is about 15-100 μm thick. Since the conductive layer164 is substantially smooth and flat, the dielectric layer will also besmooth. Moreover, the dielectric layer 168, and any adhesive layer usedto connect the dielectric layer 168 with the conductive layer 164, willbe of substantially uniform thickness.

Once the dielectric layer 168 is positioned correctly, holes 122 a, 122b, and 122 c may be created in the dielectric layer 168, as shown inFIG. 1E. The holes 122 a, 122 b, and 122 c may be created by physicallyor chemically etching away unwanted portions of the dielectric layer168. The holes can be formed by conventional techniques. Examples ofplasma etching techniques for LCP layers can be found in the article“Micromachining Techniques for Liquid Crystal Polymer,” Wang et al., the14th IEEE International Conference on Micro Electro Mechanical Systems,2001, MEMS 2001, Interlaken, Switzerland, pages 126-130, this referencebeing herewith incorporated by reference herein. Other techniques suchas laser ablation can be used. Preferably, the holes 122 a, 122 b, and122 c are aligned with the circular terminal-forming portions 132 a, 132b, and 132 c of islands 124 a, 124 b, and 124 c, formed from the etchresistant layer 162.

Referring to FIG. 1F, next the base layer 160 is etched or otherwisetreated to form a recess 26 in the base layer 160, leaving a metallicwall 20. The metallic wall 20 forms a recess 26 that gives access to theislands 124 a, 124 b, and 124 c. In addition, the metallic wall 20 willsurround the islands 124 a, 124 b, and 124 c. The metal wall 20 has abase 141 formed by etching conductive layer 164 as discussed below.

The dimensions of the metallic wall 20 can vary over a significantrange, depending on the dimensions of the microelectronic device thathas to be packaged. Typically the height of the wall on top of thesurface of the conductive layer 164 is in a range from 50 μm to 500 μm.The thickness of the metallic wall 20 measured in a direction parallelto the layers 160, 162 most commonly is in a range of 250-5000 μm. Inother embodiments, the metallic walls 20 may be tapered so that theirthickness varies with height, or slanted.

During or after the formation of metallic walls 20, a pattern is formedin conductive layer 164. For instance, during the etching of the baselayer 160, the etching process is allowed to continue past theetch-resistant layer 162 and into the conductive layer 164 in thoseregions of the conductive layer 164 which are not covered by the islands124 a, 124 b, 124 c of the etch-resistant layer. The material chosen forthe etching process does not substantially react with the material inthe etch-resistant layer 162. Copper etch that does not attack a nickeletch resistant layer 162 can be used, for example an etching materialbased on Ammonium or Ammonium Chloride. Thus, as shown in FIG. 1G, as aresult of the etching process, a second skeleton pattern is created inthe conductive layer 164, which essentially is a copy of the skeletonpattern 129 of etch-resistant layer 162, thereby forming second islands127 a, 127 b, 127 c in contact with the islands 124 a, 124 b, 124 c ofthe etch-resistant layer and in contact with the dielectric layer 18.Although not shown seen in FIG. 1G, the second islands 127 a, 127 b, 127c also include circular terminal-forming portions corresponding tocircular portions 132 (FIG. 1I) in the etch-resistant layer and elongatetrace-forming portions corresponding to the trace-forming portions 130.The circular portions of the second islands 127 a, 127 b, 127 c formterminals 22, and the elongate portions of the second islands formtraces 24 extending from the terminals.

Optionally, the remaining exposed portions of the etch-resistant layer,such as islands 124 a, 124 b, and 124 c, can be removed at this stage ofthe process, for example, by a step of etching with an etchant that doesnot attack the dielectric layer 168.

With reference still to FIG. 1H, a solder mask layer 143 is depositedonto the upper surfaces and the side walls of the terminals 22 andtraces 24 and onto those portions of the upper surface 31 of thedielectric layer 168 that are not covered by the terminals 22 and traces24. The solder mask layer 84 may be applied by draping a preexistinglayer of a photoimageable masking material in a soft, pliable conditionover the terminals and traces and portions of the dielectric layer 168,or by applying the photoimageable material in liquid form. The soldermask layer 143 conforms to exposed surfaces of the contact pads 24 andto the upper surface 31 of the dielectric layer 168 that are exposed.The solder mask layer is selectively exposed to light, so as toselectively cure or degrade only portions of the layer. Subsequently,the portions of the solder mask layer 143 that lie on connectionportions 27 of the traces 24 are removed.

As illustrated in FIGS. 1H and 1I, a chip carrier structure 16 togetherwith the metallic walls 20 is obtained. An outline 21 of the placementof the microelectronic device is shown on the chip carrier 16. Theoutline may not be physically present in the real chip carrier 16, butis still shown in FIG. 1I for illustrative purposes.

In a next step, a microelectronic device 28 (FIG. 2) is mounted into therecess 26 defined by each chip carrier 16 and the associated metallicwall 20, thereby forming a microelectronic package 10. Themicroelectronic device can be mounted by reflow soldering or any othermethod of electrically connecting the contacts 32 of the device to theconnection portion 27 of the traces 24. Before soldering themicroelectronic device 28 to the chip carrier 16, device 28 has to bealigned, for example, by the use of a machine vision system for checkingthe position of the device 28 and comparing the position of the devicewith the connection portions 27 or the location of the metallic walls20, and by use of a robotic arm to precisely position the device 28inside the package 10. The device 28 has to be aligned so that thedevice pads 32 match the corresponding connection portions 27 of thecontact pads 24. Alternatively, a stud-bumped electronic device may bebonded to the connection portions 27 of contact pads 24. In othervariants, electronic device may be disposed in recess 26 with itscontacts facing upwardly away from the dielectric layer, and thesecontacts may be wire-bonded to the connection portions 27 of contactpads 24.

In the manufacturing step of placing the device 28 into the chip carrier16, an adhesive (not shown) optionally can be put onto the upper surfaceof the chip carrier 16 and the contact pads 24, to improve adhesion ofthe microelectronic device 28 to the chip carrier 16. The space 42between the device 28 and the chip carrier would thereby besubstantially filled out with the adhesive. The adhesive material may bea material which remains compliant after curing. For example, a siliconegel or compliant epoxy could be used. In other embodiments, space 42 maybe unfilled. The solder or other connections may support the device 28spaced above chip carrier 16.

After the step of attaching the microelectronic device 28 to the chipcarrier 16, a step of attaching a metal lid or cover 34 to the metallicwall 20 is performed. The lid 34 forms a hermetic or near-hermeticenclosure of the semiconductor chip package. The hermetic ornear-hermetic seal can be achieved by soldering the metal lid 34 ontothe metallic wall 20. Other methods of attaching the lid 34 to themetallic wall 20 can be used. For example, the lid 34 could be sealed byusing a laser welder. To allow a hermetic seal between the lid 34 andthe upper surfaces of the metallic wall 20, the corresponding connectingsurfaces of lid 34 and wall 20 should be matching, or be substantiallyflat. Any non-matching portions of the two surfaces forming thisinterconnection can be filled, for example, by solder or another sealingmaterial.

The lower surfaces of the terminals 22 are exposed through holes 122 inthe dielectric layer. Terminals 22 can be equipped with solder balls 38(FIG. 1), solder paste, or other electrically conductive bondingmaterial. The bonding material serves to connect the package 10 to anexternal substrate, such as a printed circuit panel (not shown) or otherelement that supports the package 10 and provides electrically connectsterminals 22 and a larger circuit. The method steps used to apply solderballs 38 onto the terminals 22 can be essentially the same as used insurface mounting of a microelectronic device to a circuit panel.

All of the steps discussed above for forming the chip carrier may beperformed while the various layers are in the form of a large sheet ortape, so as to form a large sheet or tape incorporating numerous chipcarriers. Likewise, the steps used to mount the microelectronic deviceto each chip carrier, attach the lid and attach the solder balls may beperformed while the chip carriers remain in the form of a sheet or tape.The sheet or tape may be severed to yield individual packages.Alternatively, the sheet or tape may be severed at any time during theprocess, and subsequent process steps may be performed on individualunits.

The finished semiconductor package 10 made by the process discussedabove includes a microelectronic device 28 mounted to a chip carrier 16incorporating a dielectric layer 18 and terminals 22. Dielectric layer18 is made of a flexible material with very low moisture and gaspermeability. The microelectronic device 28 can be a semiconductor chipor die, or a piezoelectric element such as a filter element for surfaceacoustic wave (SAW), other types of radio frequency (RF) filters,sensitive sensor elements such as an image sensor, micromechanicalsystems, micro-electro-mechanical systems (MEMS) or any othermicroelectronic device.

In the embodiment shown in FIG. 2, the terminals 22 are offset from thecontacts 32 of the microelectronic device 28 in a horizontal direction,and are electrically connected together by means of traces 24. Dependingon the application, there may be no offset at all, or can also be up to2 mm. The offset together with the flexibility of the traces 24 formedby thin layers of metal, and the flexibility of the dielectric layer 18allow some independent vertical displacement of each terminals 22relative to the chip. The space 42 between the microelectronic device 28and the terminals 22 facilitates flexing of the chip carrier 16.

This flexibility of the above described structure allows independentmovement of the terminals 22, for example, to facilitate engagement ofthe solder balls 38 with contact pads on a circuit board (not shown)despite irregularities in the circuit board or the package, such aswarpage of the circuit board. Movability of the terminals also presentsadvantages in connection reliability, if the package is subjected tothermal cycles and the consequent thermal expansion of the package, thecircuit board and the chip. Additionally, this movability of theterminals also facilitates simultaneous engagement of the pluralterminals with a test fixture, and thus simplifies testing of thepackage. In the embodiment discussed above, the terminals 22 aredisposed on the top surface 31 of dielectric layer 18, and are exposedat the bottom surface 33 of the dielectric through holes 122 in thedielectric layer. The terminals have horizontal dimensions larger thanthe holes, so that the terminals effectively seal the holes. To provideeffective sealing, the diameter of each terminal 22 desirably is about300 μm larger than the diameter of the associated hole, at least about100 μm.

The packaged microelectronic device 28 fits into the recess 26 formed bythe inner sides of the metallic wall 20 and the upper surface 31 of thechip carrier 16. The free space between the metallic walls 20 and themicroelectronic device 28 preferably is minimal so as to reduce overallpackage size, but sufficient to permit placement and mechanicalalignment of the microelectronic device onto the connection portions. Ina variant, the inner dimensions of the metallic walls 20 are made so asto fit closely with the device 28. In this variant, the device 28 isaligned with the connection portion 27 by engaging the edges of thedevice with the walls 20. Thus, no further mechanical alignment isnecessary.

Package 10 as a whole desirably has a helium leak rate of around 10⁻⁵atm cm³/sec or less, and therefore, is near-hermetically sealed underthe standard MIL-STD-882.

Package 10 desirably is thin, and thereby has a very low packagingheight on a circuit board. The thickness of the package, from the bottomsurface 33 of the dielectric layer 18 to the top of lid 34 (without anyprotruding elements of the connections 22 or any solder balls 38attached thereto) can be between 100 μm to 300 μm, more preferablybetween 130 μm to 300 μm. It is possible that the thickness of thepackage may exceed the thickness of the microelectronic device itself by200 μm or less, more preferably 100 μm or less.

A manufacturing method according to a further embodiment (FIGS. 3A-3F)is generally similar to the method discussed above with reference toFIGS. 1A-1I. However, the subassembly or composite metal plate 66 usedin this method includes a bottom layer 64 made of a conductive material,an intermediate etch-resistant layer 62 and a top layer 60 made of aconductive material is provided. The top and bottom layers 60, 64 mayinclude electrically conductive materials such as copper as discussedabove for forming the walls and the conductive features of the chipcarrier. The intermediate etch-resistant layer 62 may include materialssuch as nickel resistant to etching by an etchant which attaches layers60 and 64. Referring to FIG. 3B, the bottom layer 64 of metallic plate66 is etched to remove portions 25 of the bottom layer 64 so as to leaveonly the desired conductive features of the chip carrier, such as traces124 and terminals 123, the traces having connection portions 127 attheir ends remote from terminals 123.

Referring to FIGS. 3B and 3C, a flexible dielectric layer 68, such as anLCP film is assembled with the etch-resistant layer 62 or formed inplace on the etch-resistant layer 62, so that the conductive features123, 124 are embedded with the LCP material. An upper surface 31 of thedielectric layer 68 faces toward the etch-resistant layer 62 and a lowersurface 33 of the dielectric layer 68 faces away from the etch-resistantlayer 62. The dielectric layer 68 may be fabricated by coating adielectric layer such as LCP onto the etch-resistant layer 62 and aroundand on the conductive features 123, 124.

Referring to FIG. 3D, once the dielectric layer 68 is in place, aportion of the top metal layer 60 is etched to form the metallic walls120 forming a recess 126.

Referring to FIG. 3E, the etch-resistant layer 62 that remains insidethe recess 126 is removed, leaving conductive features including traces124 and terminals 123 having their upper surfaces flush with uppersurface 131 of the dielectric layer 118. The conductive features aretherefore substantially embedded into the dielectric layer. Optionally,a solder mask layer (not shown) can be placed on top of the uppersurface 131 of the dielectric layer 118 and on top of the conductivefeatures, and patterned to omit the solder mask layer from theconnection portions 127 of the traces 124, if desired. In FIG. 3F, thedielectric layer 118 is further processed to form openings 122 inalignment with at least some of the terminals 123, and thus leaveterminals 123 exposed at the bottom surface 133 of the dielectric layer.

The resulting chip carrier 116 may then be assembled with amicroelectronic device 28 as discussed above.

In another embodiment of the microelectronic package, as shown in FIGS.4 and 5, after forming the recess 226 and metallic wall 220, and afterthe connection of a device 228 to the traces and terminals, theremaining portion of the recess 226 can be filled with a mold compoundor a potting material 230. The metallic wall 220 thereby has a firstfunction of forming sidewalls for the semiconductor package, and alsohas a second function of working as a dam for the potting material 230,while the potting material 230 is in its liquid state. During such astep of manufacturing the semiconductor package, the mold compound orpotting material can be poured into the recess 226, while the chipcarrier is held horizontally. The chip carrier 216 preferably is held ina horizontal position until the potting material 230 is hardened. It ispossible to perform such a step in a heated chamber, to reduce theviscosity of the potting material and to decrease hardening time.

The potting material 230 filled into the recess will level out over theentire recess 226. The potting material 230, once hardened, can providean additional mechanical attachment of the device 228 to the dielectricelement of the package. The potting material can also provide improvedthermal conductivity between the device 228 and elements of the packageincluding the side walls 220 and the chip carrier 216. The pottingmaterial may be a material with high thermal conductivity, such as anelectrically insulating urethane, epoxy, silicon or other resincomposition with a thermally-conductive filler. The recess 26 can beentirely filled with the mold compound or potting material, and thepotting material can cover the surface of the microelectronic device, asshown in FIG. 5.

In a variant of this approach, the lower portion of the recess 226,including the space 242 between the device 228 and the chip carrier 216may be filled with an adhesive or non-adhesive material, such as arelatively soft filler or first potting material, whereas the remainingspace in the recess can be filled with a second potting material havinghigher thermal conductivity. The second potting material may be stifferthan the first potting material.

The step of filling of the recess 226 with the potting material can beperformed under vacuum or in an inert atmosphere to eliminate inclusionof oxygen and other gases in the semiconductor package. In a furthervariant, the lid 234 may be applied and sealed while the vacuum or inertatmosphere is maintained. In yet another variant, the lid 234 maycontact the upper surface of device 228, the potting material 226, orboth. This arrangement provides even greater thermal conductivity. Inyet another variant, the step of applying and sealing the lid underinert gas or under vacuum can be performed without using an encapsulantor potting compound, so that the space 230 is filled with an inert gasor is under vacuum after sealing the lid.

In a package according to another embodiment, the metallic walls 320have a height equal to, or less than, the height of the upper surface ofthe microelectronic device 328, as illustrated in the embodiment of FIG.8. The height of the metallic wall 320 and the height of conductivefeatures 324 may be substantially equal. For example, the metallic wall320 and the conductive features 324 may be formed from the same metallayer by etching this metal layer to form both the wall and theconductive features. In this variant, the lid 334 enclosing thesemiconductor package would not be flat, but would have a bent shape ora U-shape from a cross-sectional view, so that the recess 326 enclosingthe microelectronic device would be substantially formed by the lid 334,and not by the chip carrier 316 and the walls 320. In a further variant,the height of the metallic walls 320 and the dimensions of the lid 334are chosen so that the lid 334 to touches the microelectronic device 328when the lid is in place on walls 320, thereby improving thermalconductivity between the upper surface of the device and the lid.

In yet another variant, an element with high thermal conductivity suchas a thermally conductive paste or grease, or a metallic element ispositioned on the upper surface of the microelectronic device beforeclosing the package with the lid. The thermally conductive elementdesirably covers a large portion of the device upper surface. In yetanother variant, the microelectronic device may be soldered to the lid.

In the embodiment of FIG. 6, the terminals 323 are in the form ofpillars or posts which protrude downwardly out of the dielectric layer316. The posts are made of electrically conductive material. When thepackage is mounted to a circuit panel, the bottom tips of posts 323 maybe soldered to connection portions of the wiring board. Posts 323 may beformed integrally with the conductive elements 323 as, for example, byusing a multi-layer metallic structure and etching one of the layers toform the posts. Terminals of this type can be used in the otherembodiments discussed herein.

In the embodiment shown in FIG. 7, the metallic lid discussed above isreplaced by a lid 457 which is formed from glass or other materialtransparent to light. This arrangement can be used, for example, for thepackaging of any microelectronic device that requires light, such asphotodiode sensor elements, CCD and CMOS image sensors, etc., or for anymicroelectronic device which emits light, such as small display devices.In this embodiment as well, the enclosure provided by the lid and wallskeeps moisture and other contaminants out of the package, and thusmaintains the characteristics of the image sensor during use. Thisarrangement can be used, for example, in a digital camera or in acamera-equipped cellular telephone. For example, an image sensor 429 canbe flip-chip or wire-bond packaged into the recess 426. The glass lid457 is sealed to the top edges of walls 430 using a sealing material 445that provides a hermetic or near-hermetic connection interface betweenthe glass lid 457 and the upper surface of the walls 430.

In the embodiment of FIG. 7, the conductive elements 424 extendoutwardly from the location of the device pads 432, and connectionportions 427, to terminals 422, so that the terminals 422 are disposedoutside of the area covered by the microelectronic device. Sucharrangement of the conductive elements is referred to as a “fan-out”design. In this arrangement, and in the arrangements discussed above,the pitch of the terminals can be bigger than the pitch of the devicepads of the microelectronic device. In the opposite arrangement,referred to as a fan-in design, the conductive elements extend inwardlyto the terminals, so that the terminals are disposed within the outlineof the microelectronic device. Such an arrangement reduces thehorizontal dimensions of the package 10. In other embodiments, theterminals may be aligned with the pads of the microelectronic devicewithout a horizontal offset

In the variant depicted in FIG. 8, the terminal 522 includes a pad 525on the top or inside surface of the dielectric layer 518 and a pad 558on the outside or bottom surface of the dielectric layer, as well as ashaft portion extending between these pads and extending through a hole502 in the dielectric layer. Both of these pads have horizontaldimensions greater than the dimensions of hole 502. For example, pads525, 558 may be about 50 μm-150 μm larger in diameter than hole 502. Thepads increase the length of a potential leakage or diffusion path formoisture and gases through the dielectric layer. The pads 558 on thebottom surface can be soldered or otherwise bonded to a substrate orexternal wiring board. In yet another variant, the pads 558 on thebottom surface of the dielectric layer can be replaced by pins or postswhich have larger diameter than the holes 502. In a further variant(FIG. 9), the side walls 559 of the holes in the dielectric layer areconvoluted, and the shaft portions of the terminals are also convoluted.The convoluted surface 559 increases the leakage path, and therebyimproves the hermeticity of the package.

In yet another variant, the surface of the dielectric layer can beconvoluted at the location where the wall, such as wall 20 (FIG. 2)joins the dielectric layer. Here again, the convolutions will providelonger leakage paths.

As shown in FIG. 10, a metallic shielding layer 670 is provided on theupper surface of the dielectric layer 618. Shielding layer 670 iselectrically isolated from all or most of the conductive elements 624,as by gaps 625 surrounding the conductive elements. The shielding layerprovides electromagnetic shielding, such as radio frequency (RF)shielding. Additionally, the shielding layer reduces gas permeation intothe package. Such a shielding layer can be formed from the sameconductive layer used to make the conductive elements. Merely by way ofexample, the gaps 625 between shielding layer 670 and the conductiveelements 624 can be in the range of 5 μm to 100 μm wise. The shieldinglayer can also electrically contact those conductive elements 624 whichserve as the ground or power terminals and contact pads for themicroelectronic device. The shielding layer 670 may contact the sidewalls 620 of the package. The shielding layer may be covered by a soldermask layer as discussed above to avoid solder bridging when a device issoldered to the conductive elements 624.

To provide still further electromagnetic shielding, permeationresistance, or both, the chip carrier may include a substantiallycontinuous metallic plane, such as a ground plane, extending on a lowersurface of the chip carrier facing away from the microelectronic device.Further metallic layers or particles or particles may be provided insidethe dielectric layer of the chip carrier. For example, the dielectriclayer may be made in a form of a multilayer structure with conductivelayers embedded therein.

In the embodiments discussed above, the dielectric layer is the samesize as the outer dimensions of the wall. However, the dielectric layermay project outwardly beyond the wall, so that additional components canbe mounted on the outwardly-projecting portions of the dielectric layer.These components may be elements which do not require the protectionafforded by the wall and lid. Also, although the walls depicted in thedrawing enclose rectangular regions, the walls may have any shape.

Although the aspects herein have been described with reference toparticular embodiments, it is to be understood that these embodimentsare merely illustrative of the principles and applications of thevarious embodiments. It is therefore to be understood that numerousmodifications may be made to the illustrative embodiments and that otherarrangements may be devised without departing from the spirit and scopeof the present invention as defined by the appended claims.

1. A method of making a microelectronic package comprising the steps of:(a) providing a dielectric layer having top and bottom surfaces,terminals exposed at the bottom surface, and a wall projecting upwardlyfrom the top surface; (b) mounting a microelectronic element over aregion of the top surface surrounded by the wall and electricallyconnecting the microelectronic element to at least some of theterminals; and (c) bonding a lid to the wall so that the lid extendsover the microelectronic element and the microelectronic element.
 2. Themethod of making a microelectronic package according to claim 1, whereinthe bonding step includes metallurgically bonding the metallic lid tothe wall.
 3. The method of making a microelectronic package according toclaim 1, further comprising: filling a mold compound into the regionafter said mounting by using the wall as a dam for the mold compoundbeing in a liquid state.
 4. A method of making a microelectronic chipcarrier, comprising the steps of: (a) providing a composite metallicplate including a base layer of a metal and a conductive layer; (b)etching the base layer to form a wall; (c) etching the conductive layerto separate the conductive layer into individual conductive elements;and (d) uniting the conductive elements and wall with a dielectric layerso that the wall projects upwardly away from the dielectric layer andencircle a region of the dielectric layer, and so that the conductiveelements are carried on the region of the dielectric layer.
 5. Themethod as claimed in claim 4 wherein the step of uniting the conductiveelements and the wall with the dielectric layer includes uniting thedielectric layer with the composite metallic plate after etching theconductive layer to separate the conductive layer into individualconductive elements, and before etching the base layer to form the wall.6. The method as claimed in claim 4 wherein the step of uniting theconductive elements and the wall with the dielectric layer is performedby uniting the dielectric layer with the composite metallic plate beforeetching the base layer to form the wall, and wherein the step of etchingthe conductive layer is performed during or after etching the base layerto form the wall.
 7. The method as claimed in claim 6 wherein the stepof providing the composite metallic plate includes providing islands ofan etch-resistant material between the base layer and the conductivelayer in a pattern corresponding to the conductive elements to beformed, and wherein the step of etching the conductive layer includesexposing a the conductive layer to an etchant so that the islands ofetch-resistant material protect portions of the conductive layer fromthe etchant and portions of the conductive layer between the islands areremoved.
 8. The method as claimed in claim 4 wherein the conductiveelements include terminals, the method further comprising forming holesin the dielectric layer so that the terminals are exposed at a bottomsurface of the dielectric layer facing away from the wall.